1. Field of the Invention
This invention relates generally to an image sensor. In particular, it relates to an image sensor with a vertically integrated PIN thin-film photodiode.
2. Description of the Related Art
Solid state image sensors, which are used in applications such as digital cameras, are currently available in numerous forms. Charge coupled devices (CCD) and CMOS image sensors, for example, are based on a two dimensional array of pixels. Each pixel contains a light sensing device that is capable of converting an optical image into an electronic signal. When photons strike the photoactive region of the array, free charge carriers are generated in an amount that is linearly proportional to the incident photon radiation. The photon generated charge carriers are collected and moved to output circuitry for processing. The pixels are typically disposed in rows and columns to form the array.
Integration of the image sensors with signal processing circuitry has become more important because integration enables miniaturization and simplification of imaging systems. Integration of image sensors along with analog and digital signal processing circuitry allows electronic imaging systems to be low cost, compact and require low power consumption.
Typical prior art CMOS image sensors in use rely on a lateral integration of the photodetector and the pixel electronics. In a laterally integrated CMOS image sensor, the photodetector and the CMOS circuitry are fabricated next to each other on the silicon substrate. Thus, additional lateral area (“real estate”) is required for the lateral integration of the photodetector with the CMOS circuitry. This can reduce the area fill factor and limit the possible resolution. Furthermore, it is difficult to optimize the process technology for both the CMOS transistor and for the photodiode at the same time. For example, while the design of fast CMOS circuits demands the use of shallow junctions with very low sheet resistance, these junctions are totally inconsistent for use as a photodiode. Also, when additional on-chip functions are added to the sensors, either the pixel size will increase to maintain the sensitivity of the sensor or the area required for the photodiode will decrease to maintain the pixel size. If the pixel size increases to maintain the sensitivity, the resolution of the sensor will decrease. If the photodiode area decreases to maintain the pixel size, the sensitivity of the sensor may decrease.
In a laterally integrated CMOS image sensor, as the pixel size is shrunk and multi-layer metal is used to increase circuit density and realize camera-on-chip, the photosensitivity of the image sensor is degraded due to light scattering, low fill factor (which is the ratio of photodetector area to pixel area) and destructive difference (different refraction index, n, dielectric film used in ILD/IMD).
Recently, vertically integrated thin film photodiode has been used to increase photosensitivity.
In U.S. Pat. No. 6,288,435 to Ping Mei et al, the occurrence of vertical leakage current if the metal line (contacting the data line) is exposed to the intrinsic amorphous silicon is discussed, and a continuous amorphous silicon layer sensors using a wider N+ amorphous silicon layer sealing the metal line or using a doped polysilicon back contact to reduce vertical leakage current is taught. However, the former method needs another mask to generate a wider N+ amorphous silicon layer, and the latter method increases the electric resistance between the PIN element and the data line. Moreover, a multi-layer metal interconnection structure is also needed as the pixel size is shrunk, so as to realize camera-on-chip.
U.S. Pat. No. 6,018,187 to Jeremy A. Theil et al discloses that a conductive lead connected between a bias circuit and the transparent conductive layer contacting the PIN photo diodes is not a reliable connection structure. An elevated PIN diode active pixel sensor including a reliable interconnection structure between the pixel sensor and the substrate is therefore taught. The transparent conductive layer is electrically connected to the substrate through a conductive plug and a bonding pad is designed. Further, an inner metal section is optionally formed between each pixel electrode and the underlying conductive plug to lower resistance to obtain better current collection. However, if the inner metal section is formed to lower resistance between the PIN element and the underlying interconnection, another processing step is needed.
Accordingly, the present invention pertains to the vertical integration of photodetectors with CMOS circuitry with reliable structure, fewer masks and decreased process cost.